High-level modeling and synthesis for embedded FPGAs.
Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid, Tobias G. Noll
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Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid, Tobias G. Noll
Browse the full DATE paper archive.