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Paper
An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier.
Malte Baesler
,
Sven-Ole Voigt
,
Thomas Teufel
Venue
B
FPL
Year
2010
Proceedings
FPL
DBLP record
conf/fpl/BaeslerVT10 ↗
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