An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU.

Yasushi Ooi, Osamu Ohnishi, Yutaka Yokoyama, Yoichi Katayama, Masayuki Mizuno, Masakazu Yamashina, Hideo Takano, Naoya Hayashi, Ichiro Tamitani

Browse the full ICASSP paper archive.