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A 40 μV VRipple, 0.1-ps FoM Output-Capacitor-Less Fully Time-Domain Digital LDO With a VCO-Assisted Dual Loop.

Guanzhe Hu, Shengping Lv, Yufei Song, Peng Zhang, Wen Jia, Fei Chen, Shuqiang Lu, Zhihua Wang, Hanjun Jiang

VenueCISCAS
Year2026
ProceedingsISCAS

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