Skip to content

CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC.

Xihao Liang, Yujie Wang, Xupengkai Lu, Lang Feng, Jixiang Zhu, Ying Wang, Yinhe Han

VenueCISCAS
Year2025
ProceedingsISCAS

Browse the full ISCAS paper archive.