CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC.
Xihao Liang, Yujie Wang, Xupengkai Lu, Lang Feng, Jixiang Zhu, Ying Wang, Yinhe Han
Browse the full ISCAS paper archive.
Xihao Liang, Yujie Wang, Xupengkai Lu, Lang Feng, Jixiang Zhu, Ying Wang, Yinhe Han
Browse the full ISCAS paper archive.