| 2026 | ACL | ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning. | Zhirong Chen, Kaiyan Chang, Zhuolin Li, Cangyuan Li, Xinyang He, Chujie Chen, Mengdi Wang, Haobo Xu, Yinhe Han, Huawei Li, Ying Wang |
| 2026 | ASPLOS | Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference. | Yiqi Liu, Yudong Pan, Mengdi Wang, Shixin Zhao, Haonan Zhu, Yinhe Han, Lei Zhang, Ying Wang |
| 2026 | ASPLOS | I/O Analysis is All You Need: An I/O Analysis for Long-Sequence Attention. | Xiaoyang Lu, Boyu Long, Xiaoming Chen, Yinhe Han, Xian-He Sun |
| 2026 | DATE | FHEx: Transforming Generic Compute Chips into Secure FHE Engines via a Hardware-software Co-designed Framework. | Yibo Du, Ying Wang, Mengdi Wang, Cangyuan Li, Lian Liu, Hui Li, Kai Zhang, Yinhe Han |
| 2026 | DATE | From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design. | Jinxin Yu, Yudong Pan, Mengdi Wang, Huawei Li, Yinhe Han, Xiaowei Li, Ying Wang |
| 2026 | DATE | MACAM: A Flexible Computing-in-Memory Accelerator for Sparse Matrix-Dense Vector Multiplication. | Xiaoyu Zhang, Rui Liu, Zerun Li, Yinhe Han, Xiaoming Chen |
| 2026 | ISCA | AutoFHE: An Automatic Hardware Generation Framework for Domain-Specific FHE Accelerators. | Yibo Du, Cangyuan Li, Bing Li, Mengdi Wang, Lian Liu, Shixin Zhao, Yinhe Han, Ying Wang |
| 2026 | ISCA | Unlocking Pipeline Parallelism for Bootstrapping: A Pipelined Multi-Chiplet TFHE Accelerator. | Yibo Du, Mengdi Wang, Cangyuan Li, Yinhe Han, Ying Wang |
| 2026 | ISCA | ConBin: a Performance-Convergence Framework for Wafer-Scale Chip Binning. | Huiqing Xu, Mengdi Wang, Yinhe Han, Ying Wang |
| 2026 | ISCAS | GPA: A General-Purpose In-Memory Computing Accelerator. | Xiaoyu Zhang, Zerun Li, Rui Liu, Libo Shen, Boyu Long, Xueqi Li, Yinhe Han, Xiaoming Chen |
| 2025 | ASPDAC | RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. | Kun Wang, Kaiyan Chang, Mengdi Wang, Xingqi Zou, Haobo Xu, Yinhe Han, Ying Wang |
| 2025 | ASPLOS | COMET: Towards Practical W4A4KV4 LLMs Serving. | Lian Liu, Long Cheng, Haimeng Ren, Zhaohui Xu, Yudong Pan, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang |
| 2025 | ASPLOS | Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators. | Shixin Zhao, Yuming Li, Bing Li, Yintao He, Mengdi Wang, Yinhe Han, Ying Wang |
| 2025 | DAC | CIM-BLAS: Computing-in-Memory Accelerator for BLAS. | Rui Liu, Zerun Li, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang |
| 2025 | HPCA | Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. | Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang |
| 2025 | HPCA | LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding. | Haoran Wang, Yuming Li, Haobo Xu, Ying Wang, Liqi Liu, Jun Yang, Yinhe Han |
| 2025 | ICCAD | CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits. | Yu Chen, Yilun Zhao, Bing Li, He Li, Mengdi Wang, Yinhe Han, Ying Wang |
| 2025 | ICCAD | RTPU: Unifying Non-Private and Private Inference with Reconfigurable Architecture. | Fuping Li, Ying Wang, Yinghao Yang, Jingxuan Li, Yibo Du, Huawei Li, Yinhe Han, Hang Lu, Xiaowei Li |
| 2025 | ICCD | FlexIO: A Scalable IO Chiplet Architecture with Flexible Memory Controller Mapping. | Junpei Huang, Haobo Xu, Ying Wang, Yinhe Han |
| 2025 | ICML | BaWA: Automatic Optimizing Pruning Metric for Large Language Models with Balanced Weight and Activation. | Lian Liu, Xiandong Zhao, Guanchen Li, Dong Li, Mengdi Wang, Yinhe Han, Xiaowei Li, Ying Wang |
| 2025 | IROS | CA | Xuebin Meng, Wei Li, Yu Hu, Yinhe Han |
| 2025 | ISCA | Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation. | Yiyang Huang, Yuhui Hao, Bo Yu, Feng Yan, Yuxin Yang, Feng Min, Yinhe Han, Lin Ma, Shaoshan Liu, Qiang Liu, Yiming Gan |
| 2025 | ISCAS | CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC. | Xihao Liang, Yujie Wang, Xupengkai Lu, Lang Feng, Jixiang Zhu, Ying Wang, Yinhe Han |
| 2025 | ICRA | KARMA: Augmenting Embodied AI Agents with Long-and-Short Term Memory Systems. | Zixuan Wang, Bo Yu, Junzhe Zhao, Wenhao Sun, Sai Hou, Shuai Liang, Xing Hu, Yinhe Han, Yiming Gan |
| 2025 | MICRO | Distributed-HISQ: A Distributed Quantum Control Architecture. | Yilun Zhao, Kangding Zhao, Peng Zhou, Dingdong Liu, Tingyu Luo, Yuzhen Zheng, Peng Luo, Shun Hu, Jin Lin, Cheng Guo, Yinhe Han, Ying Wang, Mingtang Deng, Junjie Wu, Xiang Fu |
| 2024 | ASPDAC | Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. | Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2024 | ASPLOS | ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications. | Yuhui Hao, Yiming Gan, Bo Yu, Qiang Liu, Yinhe Han, Zishen Wan, Shaoshan Liu |
| 2024 | ASPLOS | ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations. | Xiaoyang Lu, Boyu Long, Xiaoming Chen, Yinhe Han, Xian-He Sun |
| 2024 | ASPLOS | PrimePar: Efficient Spatial-temporal Tensor Partitioning for Large Transformer Model Training. | Haoran Wang, Lei Wang, Haobo Xu, Ying Wang, Yuming Li, Yinhe Han |
| 2024 | BMVC | Benchmarking and Optimizing Federated Learning with Hardware-related Metrics. | Kai Pan, Yapeng Tian, Yinhe Han, Yiming Gan |
| 2024 | DAC | Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. | Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2024 | DAC | Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. | Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2024 | DAC | Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. | Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2024 | DATE | GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. | Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2024 | DATE | PIMSYN: Synthesizing Processing-in-Memory CNN Accelerators. | Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen |
| 2024 | DATE | PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators. | Xinyu Wang, Xiaotian Sun, Yinhe Han, Xiaoming Chen |
| 2024 | ICCAD | Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. | Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang |
| 2024 | ICCD | MemSort: In-Memory Sorting Architecture. | Rui Liu, Xiaoyu Zhang, Xinyu Wang, Feng Min, Zhejian Luo, Xiaoming Chen, Yinhe Han, Minghua Tang |
| 2024 | ICCD | AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System. | Liang Yan, Xiaoyang Lu, Xiaoming Chen, Sheng Xu, Xingqi Zou, Yinhe Han, Xian-He Sun |
| 2024 | ISCAS | Accelerating Frequency-domain Convolutional Neural Networks Inference using FPGAs. | Yi Chen, Bosheng Liu, Yongqi Xu, Jigang Wu, Xiaoming Chen, Peng Liu, Qingguo Zhou, Yinhe Han |
| 2024 | MICRO | TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining. | Zerun Li, Xiaoming Chen, Yinhe Han |
| 2023 | ASPDAC | Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach. | Bosheng Liu, Hongyi Liang, Jigang Wu, Xiaoming Chen, Peng Liu, Yinhe Han |
| 2023 | DAC | APPEND: Rethinking ASIP Synthesis in the Era of AI. | Cangyuan Li, Ying Wang, Huawei Li, Yinhe Han |
| 2023 | DAC | PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators. | Xiaotian Sun, Xinyu Wang, Wanqian Li, Lei Wang, Yinhe Han, Xiaoming Chen |
| 2023 | DAC | FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator. | Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen, Yinhe Han |
| 2023 | DATE | Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. | Chengsi Gao, Ying Wang, Cheng Liu, Mengdi Wang, Weiwei Chen, Yinhe Han, Lei Zhang |
| 2023 | DATE | ENASA: Towards Edge Neural Architecture Search based on CIM acceleration. | Shixin Zhao, Songyun Qu, Ying Wang, Yinhe Han |
| 2023 | HPCA | CTA: Hardware-Software Co-design for Compressed Token Attention Mechanism. | Haoran Wang, Haobo Xu, Ying Wang, Yinhe Han |
| 2023 | ICCAD | Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis. | Boyu Long, Libo Shen, Xiaoyu Zhang, Yinhe Han, Xian-He Sun, Xiaoming Chen |
| 2023 | ICCAD | LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture. | Libo Shen, Boyu Long, Rui Liu, Xiaoyu Zhang, Yinhe Han, Xiaoming Chen |
| 2023 | ICCAD | Full State Quantum Circuit Simulation Beyond Memory Limit. | Yilun Zhao, Yu Chen, He Li, Ying Wang, Kaiyan Chang, Bingmeng Wang, Bing Li, Yinhe Han |
| 2023 | ICCD | PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. | Yibo Du, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2023 | ICCD | Hardware-Software Co-Design for Content-Based Sparse Attention. | Rui Tang, Xiaoyu Zhang, Rui Liu, Zhejian Luo, Xiaoming Chen, Yinhe Han |
| 2023 | MICRO | Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines. | Yuxin Yang, Xiaoming Chen, Yinhe Han |
| 2022 | ASPDAC | Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique. | Xiaoming Chen, Yinhe Han |
| 2022 | ASPDAC | Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems. | Zerun Li, Xiaoming Chen, Yinhe Han |
| 2022 | ASPDAC | FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. | Rui Liu, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang |
| 2022 | DAC | GraphRing: an HMC-ring based graph processing framework with optimized data movement. | Zerun Li, Xiaoming Chen, Yinhe Han |
| 2022 | HPCC | AIC-Bench: Workload Selection Methodology for Benchmarking AI Chips. | Zhenyu Quan, Xiaoming Chen, Yinhe Han |
| 2022 | HPCC | PME: Processing-in-memory Masking and Encoding for Secure NVM. | Zhiwen Xie, Yinhe Han, Xiaoming Chen |
| 2022 | ICCAD | GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. | Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2022 | ICML | AGNAS: Attention-Guided Micro and Macro-Architecture Search. | Zihao Sun, Yu Hu, Shun Lu, Longxing Yang, Jilin Mei, Yinhe Han, Xiaowei Li |
| 2022 | ICML | Searching for BurgerFormer with Micro-Meso-Macro Space Design. | Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yinhe Han, Xiaowei Li |
| 2022 | IJCNN | Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing. | Jingyu Niu, Yu Hu, Wei Li, Guangyan Huang, Yinhe Han, Xiaowei Li |
| 2022 | MICRO | DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture. | Xuyi Cai, Ying Wang, Xiaohan Ma, Yinhe Han, Lei Zhang |
| 2021 | ACML | DDSAS: Dynamic and Differentiable Space-Architecture Search. | Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yiming Zeng, Zhiping Shi, Yinhe Han, Xiaowei Li |
| 2021 | ASPDAC | FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors. | Xiaoming Chen, Yuping Wu, Yinhe Han |
| 2021 | DAC | F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM. | Bosheng Liu, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen, Yinhe Han, Peng Liu |
| 2021 | DAC | BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System. | Tao Song, Xiaoming Chen, Xiaoyu Zhang, Yinhe Han |
| 2021 | ICRA | KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry. | Wei Li, Yu Hu, Yinhe Han, Xiaowei Li |
| 2021 | ISLPED | CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications. | Liang Yan, Mingzhe Zhang, Rujia Wang, Xiaoming Chen, Xingqi Zou, Xiaoyang Lu, Yinhe Han, Xian-He Sun |
| 2020 | ASPDAC | Search-free Accelerator for Sparse Convolutional Neural Networks. | Bosheng Liu, Xiaoming Chen, Yinhe Han, Ying Wang, Jiajun Li, Haobo Xu, Xiaowei Li |
| 2020 | CVPR | Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction. | Beibei Jin, Yu Hu, Qiankun Tang, Jingyu Niu, Zhiping Shi, Yinhe Han, Xiaowei Li |
| 2020 | DAC | PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture. | Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, Li Jiang |
| 2020 | DAC | An Efficient Deep Learning Accelerator for Compressed Video Analysis. | Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li |
| 2020 | DAC | Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection. | Yuxin Yang, Xiaoming Chen, Yinhe Han |
| 2020 | HPCA | Communication Lower Bound in Convolution Accelerators. | Xiaoming Chen, Yinhe Han, Yu Wang |
| 2020 | ICCAD | DaDu Series - Fast and Efficient Robot Accelerators. | Yinhe Han, Yuxin Yang, Xiaoming Chen, Shiqi Lian |
| 2020 | SMC | Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing. | Jingyu Niu, Yu Hu, Beibei Jin, Yinhe Han, Xiaowei Li |
| 2019 | ASPDAC | Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. | Bosheng Liu, Xiaoming Chen, Ying Wang, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li |
| 2019 | ASPDAC | Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. | Jiajun Li, Ying Wang, Bosheng Liu, Yinhe Han, Xiaowei Li |
| 2019 | ASPDAC | CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. | Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xiaowei Li |
| 2019 | DAC | Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques. | Xiaoming Chen, Longxiang Yin, Bosheng Liu, Yinhe Han |
| 2019 | DAC | System-level hardware failure prediction using deep learning. | Xiaoyi Sun, Krishnendu Chakrabarty, Ruirui Huang, Yiquan Chen, Bing Zhao, Hai Cao, Yinhe Han, Xiaoyao Liang, Li Jiang |
| 2019 | ICCAD | ACG-Engine: An Inference Accelerator for Content Generative Neural Networks. | Haobo Xu, Ying Wang, Yujie Wang, Jiajun Li, Bosheng Liu, Yinhe Han |
| 2019 | ICCD | FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory Array. | Xiaoyu Zhang, Xiaoming Chen, Yinhe Han |
| 2019 | ITC | China Test Conference (CTC) - Extending the Global Test Forum to China. | Huawei Li, Xiaowei Li, Yinhe Han |
| 2018 | ASPDAC | PIMCH: Cooperative memory prefetching in processing-in-memory architecture. | Sheng Xu, Ying Wang, Yinhe Han, Xiaowei Li |
| 2018 | DAC | Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment. | Shiqi Lian, Yinhe Han, Xiaoming Chen, Ying Wang, Hang Xiao |
| 2018 | DATE | A retrospective evaluation of energy-efficient object detection solutions on embedded devices. | Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li |
| 2017 | ASPDAC | ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. | Xin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li |
| 2017 | ASPDAC | BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. | Shiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li |
| 2017 | ASPDAC | CNN-based object detection solutions for embedded heterogeneous multicore SoCs. | Cheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li |
| 2017 | DAC | Dadu: Accelerating Inverse Kinematics for High-DOF Robots. | Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun |
| 2017 | HPCA | FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. | Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li |
| 2016 | ASPDAC | ACR: Enabling computation reuse for approximate computing. | Xin He, Guihai Yan, Yinhe Han, Xiaowei Li |
| 2016 | DAC | C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. | Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li |
| 2016 | DAC | DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. | Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li |
| 2016 | DAC | DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. | Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li |
| 2015 | ASPDAC | ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. | Hang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li |
| 2015 | DAC | ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. | Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li |
| 2015 | DAC | Untitled record | Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li |
| 2015 | ISCAS | A case of precision-tunable STT-RAM memory design for approximate neural network. | Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li |
| 2014 | ASPDAC | Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints. | Song Jin, Yinhe Han, Songwei Pei |
| 2014 | ASPDAC | Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores. | Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li |
| 2014 | DATE | SuperRange: Wide operational range power delivery design for both STV and NTV computing. | Xin He, Guihai Yan, Yinhe Han, Xiaowei Li |
| 2014 | ICCAD | Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. | Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li |
| 2013 | DAC | RISO: relaxed network-on-chip isolation for cloud processors. | Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li |
| 2013 | DATE | SmartCap: user experience-oriented power adaptation for smartphone's application processor. | Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li |
| 2013 | ISCAS | Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. | Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li |
| 2012 | DATE | A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. | Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li |
| 2012 | HPCA | AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. | Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang |
| 2011 | ASPDAC | Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. | Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li |
| 2011 | ASPDAC | A resilient on-chip router design through data path salvaging. | Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li |
| 2011 | DAC | Wear rate leveling: lifetime enhancement of PRAM with endurance variation. | Jianbo Dong, Lei Zhang, Yinhe Han, Ying Wang, Xiaowei Li |
| 2011 | DATE | Eliminating data invalidation in debugging multiple-clock chips. | Jianliang Gao, Yinhe Han, Xiaowei Li |
| 2011 | DATE | Flex memory: Exploiting and managing abundant off-chip optical bandwidth. | Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2011 | ISCA | An abacus turn model for time/space-efficient reconfigurable routing. | Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li |
| 2010 | DATE | Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. | Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li |
| 2010 | DATE | Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. | Lei Zhang, Yue Yu, Jianbo Dong, Yinhe Han, Shangping Ren, Xiaowei Li |
| 2010 | ISCA | Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. | Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li |
| 2010 | ITC | nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. | Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li |
| 2010 | PRDC | Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. | Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2009 | DATE | A unified online Fault Detection scheme via checking of Stability Violation. | Guihai Yan, Yinhe Han, Xiaowei Li |
| 2009 | ISLPED | MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. | Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li |
| 2009 | PRDC | Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. | Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li |
| 2009 | PRDC | A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. | Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li |
| 2009 | VTS | A New Post-Silicon Debug Approach Based on Suspect Window. | Jianliang Gao, Yinhe Han, Xiaowei Li |
| 2008 | DATE | Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. | Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li |
| 2006 | GLOBECOM | Fast Packet Classification using Group Bit Vector. | Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han |
| 2006 | ISCAS | An on-chip combinational decompressor for reducing test data volume. | Jie Don, Yu Hu, Yinhe Han, Xiaowei Li |
| 2005 | ASPDAC | Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li |
| 2005 | ISCAS | Deterministic and low power BIST based on scan slice overlapping. | Ji Li, Yinhe Han, Xiaowei Li |
| 2005 | ISCAS | Validation analysis and test flow optimization of VLSI chip. | Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen |