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Paper
A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process.
Xiao Wang
,
Chengwei Wang
,
Fule Li
,
Zhihua Wang
Venue
C
ISCAS
Year
2018
Proceedings
ISCAS
DBLP record
conf/iscas/WangWLW18 ↗
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