| 2026 | ISCAS | A KT/C-Noise-Cancelled Charge-Sharing Sampling Pipeline ADC Front-End with Parallel Operation Timing and Substrate-Tracking Technique. | Shiang Li, Wen Jia, Jingpeng Zhou, Peng Wang, Fule Li, Zhihua Wang |
| 2025 | ISCAS | A SHA-Less Front-end Stage Structure Suitable for Time-Interleaved Pipeline ADC. | Meng Ni, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang |
| 2025 | ISCAS | A 550MHz-B and width 40dB-Gain Range Analog Baseband with Dynamic PVT Compensation Achieving 26.1 dBm OIP3 in 28-nm CMOS. | Guo Wei, Xuanyan Liu, Tian Tian, Yanshu Guo, Wenqiang Huang, Fule Li, Zhihua Wang, Hanjun Jiang |
| 2025 | ISCAS | A High-Speed High-Precision Comparator with Offset Calibration for SHA_less Pipeline ADCs. | Shuoxiong Yang, Dejian Li, Peng Wang, Fule Li, Zhihua Wang |
| 2025 | ISCAS | A Dynamic Biasing Circuit for Low-Power Push-Pull Input Buffer. | Rui Zhang, Yidong Yuan, Peng Wang, Lingxiao Shen, Fule Li, Zhihua Wang, Yi Hu, Zhenguo Li |
| 2024 | ISCAS | A Reconfigurable Continuous-Time Delta-Sigma Modulator Structure Using Hybrid Loop Filter and Time-Interleaved Quantizer. | Chen Chen, Fangzhen Jiang, Peng Wang, Yongli Chen, Yan Xiao, Fule Li, Xiang Xie |
| 2024 | ISCAS | A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs. | Yaning Wang, Zhenguo Li, Peng Wang, Yihang Cheng, Fule Li, Yi Hu, Jiali Hou, Meng Su, Mengjiao Li |
| 2023 | ISCAS | High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation. | Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang |
| 2023 | ISCAS | Current-Steering DAC Calibration Using Q-Learning. | Yaoyu Li, Yanshu Guo, Wen Jia, Fule Li, Zhihua Wang, Hanjun Jiang |
| 2023 | ISCAS | All-Digital Background Calibration of a Pipelined-SAR ADC Using the "Split ADC" Architecture. | Zhiqiang Luo, Peng Wang, Jingpeng Zhou, Fule Li |
| 2022 | ISCAS | A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs. | Haoran Wang, Junjie Jing, Fule Li |
| 2021 | ISCAS | A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC. | Peilin Yang, Fule Li, Zhihua Wang |
| 2018 | ISCAS | A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. | Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang |
| 2018 | ISCAS | A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process. | Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang |
| 2016 | ISCAS | A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs. | Xiao Wang, Fule Li, Zhihua Wang |
| 2015 | ISCAS | Charge-compensation-based reference technique for switched-capacitor ADCs. | Ya Wang, Fule Li, Chunying Xue, Zhihua Wang |
| 2013 | ISCAS | A 14-bit pipelined ADC with digital background nonlinearity calibration. | Weitao Li, Cao Sun, Fule Li, Zhihua Wang |
| 2013 | ISCAS | A merged first and second stage for low power pipelined ADC. | Changyi Yang, Weitao Li, Fule Li, Zhihua Wang |
| 2013 | ISCAS | A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue. | Lingwei Zhang, Hanjun Jiang, Fule Li, Jingjing Dong, Zhihua Wang |
| 2012 | ISCAS | A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end. | Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu |
| 2012 | ISCAS | A current-to-voltage integrator using area-efficient correlated double sampling technique. | Xuqiang Zheng, Fule Li, Xuan Wang, Chun Zhang |
| 2009 | ISCAS | A Robust Radio Frequency Identification System Enhanced with Spread Spectrum Technique. | Qiuling Zhu, Chun Zhang, Zhongqi Liu, Jingchao Wang, Fule Li, Zhihua Wang |
| 2007 | ISCAS | A Pipelined A/D Conversion Technique with Low INL and DNL. | Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongming Li, Zhihua Wang |
| 2007 | ISCAS | An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters. | Fule Li, Zhihua Wang, Dongmei Li |