A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end.
Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu
Browse the full ISCAS paper archive.
Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu
Browse the full ISCAS paper archive.