A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.
Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu
Browse the full ISCAS paper archive.
Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu
Browse the full ISCAS paper archive.