| 2019 | DDECS | Implementation of FPGA-based Accelerator for Deep Neural Networks. | Tsung-Han Tsai, Yuan-Chen Ho, Ming-Hwa Sheu |
| 2018 | ISCAS | An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. | Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu |
| 2012 | ISCAS | Low power 10-transistor full adder design based on degenerate pass transistor logic. | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
| 2012 | SMC | A robust background modeling and foreground object detection using color component analysis. | Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin, Ho-En Liao |
| 2009 | ISCAS | Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2 | Yuan-Ching Kuo, Su-Hon Lin, Ming-Hwa Sheu, Jia-You Wu, Peng-Siang Wang |
| 2008 | ISCAS | The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu |
| 2007 | ISCAS | Fast Fair Crossbar Scheduler for On-chip Router. | Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai |
| 2006 | ISCAS | A high speed and energy efficient full adder design using complementary & level restoring carry logic. | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |
| 2006 | ISCAS | The VLSI design of de-interlacing with scene change detection. | Chung-Chi Lin, Chih-Jen Wei, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw |
| 2005 | ISCAS | Directional interpolation for field-sequential stereoscopic video. | Hsien-Huang Peter Wu, Ming-Hwa Sheu, Tung-Yu Yang |
| 2005 | ISCAS | VLSI architecture design for a fast parallel label assignment in binary image. | Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang Peter Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu |
| 2003 | DSD | A Fast Additive Normalization Method for Exponential Computation. | Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu |
| 2001 | ISCAS | A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. | Ming-Hwa Sheu, Ho-En Liao, Shih Tsung Kan, Ming-Der Shieh |
| 2001 | ISCAS | VLSI architecture of extended in-place path metric update for Viterbi decoders. | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu |
| 2000 | ISCAS | An efficient approach for in-place scheduling of path metric update in Viterbi decoders. | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu |
| 1999 | ISCAS | A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. | Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu |
| 1993 | ISCAS | A High Throughput-Rate Architecture for 8*8 2-D DCT. | Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu |
| 1993 | ISCAS | An Expandable Chip Desing for Gray-scale Morphological Operations. | Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu |