Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs.
Carsten Bieser, Klaus D. Mller-Glaser
VenueCRSP
Year2006
ProceedingsIEEE International Workshop on Rapid System Prototyping
DBLP recordconf/rsp/BieserM06 ↗
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