An Approach to Mapping the Timing Behavior of VLSI Circuits on Emulators.
Pirouz Bazargan-Sabet, Laurent Vuillemin
VenueCRSP
Year2001
ProceedingsIEEE International Workshop on Rapid System Prototyping
DBLP recordconf/rsp/SabetV01 ↗
Browse the full RSP paper archive.