Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit.
Premysl Sucha, Zdenek Pohl, Zdenek Hanzlek
VenueARTAS
Year2004
ProceedingsIEEE Real-Time and Embedded Technology and Applications Symposium
DBLP recordconf/rtas/SuchaPH04 ↗
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