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Paper
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller.
Subhomoy Chattopadhyay
,
Rakesh Patel
Venue
National
VLSID
Year
2007
Proceedings
VLSI Design
DBLP record
conf/vlsid/ChattopadhyayP07 ↗
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