Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
VLSID
/
Paper
Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG).
Siva Embanath
,
Ramakrishnan Venkata
Venue
National
VLSID
Year
2006
Proceedings
VLSI Design
DBLP record
conf/vlsid/EmbanathV06 ↗
Browse the full
VLSID paper archive
.