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Paper
Multilevel Factorization Technique for Pass Transistor Logic.
Arunita Jaekel
,
Graham A. Jullien
,
Subir Bandyopadhyay
Venue
National
VLSID
Year
1996
Proceedings
VLSI Design
DBLP record
conf/vlsid/JaekelJB96 ↗
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