A 0.8V V_MIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Repeated-Pulse Wordline Suppression Scheme.
Ashish Kumar, Mohammad Aftab Alam, Gangaikondan S. Visweswaran
Browse the full VLSID paper archive.
Ashish Kumar, Mohammad Aftab Alam, Gangaikondan S. Visweswaran
Browse the full VLSID paper archive.