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Paper
Reducing Library Development Cycle Time through an Optimum Layout Create Flow.
Rituparna Mandal
,
Dibyendu Goswami
,
Arup Dash
Venue
National
VLSID
Year
2002
Proceedings
ASP-DAC/VLSI Design
DBLP record
conf/vlsid/MandalGD02 ↗
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