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A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.

Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Vasant Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar

Year2012
ProceedingsVLSI Design

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