Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
VLSID
/
Paper
Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder.
Yuanzhong Wan
,
Maitham Shams
Venue
National
VLSID
Year
2005
Proceedings
VLSI Design
DBLP record
conf/vlsid/WanS05 ↗
Browse the full
VLSID paper archive
.