Abhay S. Vidhyadharan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2019–2019
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | VLSID | An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices. | Sanjay Vidhyadharan, Ramakant Ramakant, Abhay S. Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Surya Shankar Dan |