| 2026 | DATE | VeriRepair: Toward Reliable LLM-Based RTL Repair via CoT-Supervised Multi-Objective Fine-Tuning and Hybrid Retrieval. | Lei Peng, Aijiao Cui, Yier Jin |
| 2020 | VTS | A New Secure Scan Design with PUF-based Key for Authentication. | Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li |
| 2019 | ISCAS | A New Pay-Per-Use Scheme for the Protection of FPGA IP. | Peiqi Sun, Aijiao Cui |
| 2019 | VTS | A Secure and Low-overhead Active IC Metering Scheme. | Aijiao Cui, Yan Yang, Gang Qu, Huawei Li |
| 2018 | ASPDAC | A low-overhead PUF based on parallel scan design. | Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li |
| 2018 | TrustCom | Partial Scan Design Against Scan-Based Side Channel Attacks. | Xi Chen, Zhaojun Lu, Gang Qu, Aijiao Cui |
| 2017 | ISCAS | Practical IP watermarking and fingerprinting methods for ASIC designs. | Xi Chen, Gang Qu, Aijiao Cui |
| 2017 | ISCAS | A new watermarking scheme on scan chain ordering for hard IP protection. | Xiaonan Huang, Aijiao Cui, Chip-Hong Chang |
| 2016 | ISCAS | An improved test power optimization method by insertion of linear functions. | Lucheng He, Aijiao Cui, Mengyang Li, Andr Ivanov |
| 2016 | ISCAS | A new countermeasure against scan-based side-channel attacks. | Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li |
| 2015 | ISCAS | An improved scan design for minimization of test power under routing constraint. | Aijiao Cui, Tingting Yu, Gang Qu, Mengyang Li |
| 2015 | ISCAS | A new decompressor with ordered parallel scan design for reduction of test data and test time. | Tingting Yu, Aijiao Cui, Mengyang Li, Andr Ivanov |
| 2014 | ISCAS | A low-overhead dynamic watermarking scheme on scan design for easy authentication. | Aijiao Cui, Wei Liang, Gang Qu |
| 2013 | ISCAS | A power-efficient scan tree design by exploring the Q'-D connection. | Linfeng Chen, Aijiao Cui |
| 2011 | ISCAS | A hybrid watermarking scheme for sequential functions. | Aijiao Cui, Chip-Hong Chang, Li Zhang |
| 2009 | ISCAS | An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering. | Aijiao Cui, Chip-Hong Chang |
| 2008 | ISCAS | Intellectual property authentication by watermarking scan chain in design-for-testability flow. | Aijiao Cui, Chip-Hong Chang |
| 2007 | ISCAS | Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. | Aijiao Cui, Chip-Hong Chang |
| 2006 | ISCAS | Stego-signature at logic synthesis level for digital design IP protection. | Aijiao Cui, Chip-Hong Chang |