Ajay N. Bhoj
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2009–2016
Best venue rank
National
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | VLSID | Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. | Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha |
| 2009 | ICCD | Pragmatic design of gated-diode FinFET DRAMs. | Ajay N. Bhoj, Niraj K. Jha |