Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.
Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha
Browse the full VLSID paper archive.
Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha
Browse the full VLSID paper archive.