Debajit Bhattacharya
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2013–2016
Best venue rank
National
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | VLSID | Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. | Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha |
| 2013 | VLSID | Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications. | Debajit Bhattacharya, Ashis Maity, Amit Patra |