| 2025 | CVPR | LinGen: Towards High-Resolution Minute-Length Text-to-Video Generation with Linear Computational Complexity. | Hongjie Wang, Chih-Yao Ma, Yen-Cheng Liu, Ji Hou, Tao Xu, Jialiang Wang, Felix Juefei-Xu, Yaqiao Luo, Peizhao Zhang, Tingbo Hou, Peter Vajda, Niraj K. Jha, Xiaoliang Dai |
| 2025 | ICCV | Generating, Fast and Slow: Scalable Parallel Video Generation with Video Interface Networks. | Bhishma Dedhia, David Bourgin, Krishna Kumar Singh, Yuheng Li, Yan Kang, Zhan Xu, Niraj K. Jha, Yuchen Liu |
| 2024 | CVPR | Zero-TPrune: Zero-Shot Token Pruning Through Leveraging of the Attention Graph in Pre-Trained Transformers. | Hongjie Wang, Bhishma Dedhia, Niraj K. Jha |
| 2024 | CVPR | Attention-Driven Training-Free Efficiency Enhancement of Diffusion Models. | Hongjie Wang, Difan Liu, Yan Kang, Yijun Li, Zhe Lin, Niraj K. Jha, Yuchen Liu |
| 2024 | NAACL | DynaMo: Accelerating Language Model Inference with Dynamic Multi-Token Sampling. | Shikhar Tuli, Chi-Heng Lin, Yen-Chang Hsu, Niraj K. Jha, Yilin Shen, Hongxia Jin |
| 2020 | CVPR | Dreaming to Distill: Data-Free Knowledge Transfer via DeepInversion. | Hongxu Yin, Pavlo Molchanov, Jos M. lvarez, Zhizhong Li, Arun Mallya, Derek Hoiem, Niraj K. Jha, Jan Kautz |
| 2020 | DAC | INVITED: Efficient Synthesis of Compact Deep Neural Networks. | Wenhan Xia, Hongxu Yin, Niraj K. Jha |
| 2019 | CVPR | ChamNet: Towards Efficient Network Design Through Platform-Aware Model Adaptation. | Xiaoliang Dai, Peizhao Zhang, Bichen Wu, Hongxu Yin, Fei Sun, Yanghan Wang, Marat Dukhan, Yunqing Hu, Yiming Wu, Yangqing Jia, Peter Vajda, Matt Uyttendaele, Niraj K. Jha |
| 2016 | VLSID | Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. | Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha |
| 2015 | DAC | Vibration-based secure side channel for medical devices. | Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan |
| 2015 | RC | Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions. | Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille |
| 2014 | VLSID | FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. | Sourindra Chaudhuri, Niraj K. Jha |
| 2013 | DAC | Towards trustworthy medical devices and body area networks. | Meng Zhang, Anand Raghunathan, Niraj K. Jha |
| 2013 | VLSID | Localized Heating for Building Energy Efficiency. | Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan |
| 2013 | VLSID | Emerging Frontiers in Embedded Security. | Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha |
| 2013 | VLSID | Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery. | Neeraj Mishra, Niraj K. Jha, Santanu Kapat, Amit Patra |
| 2013 | VLSID | Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. | Yang Yang, Niraj K. Jha |
| 2013 | VLSID | Energy-efficient and Secure Sensor Data Transmission Using Encompression. | Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha |
| 2012 | DATE | Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. | Mohammed Shoaib, Niraj K. Jha, Naveen Verma |
| 2012 | VLSID | Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. | Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha |
| 2011 | DAC | CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. | Chun-Yi Lee, Niraj K. Jha |
| 2011 | DAC | A low-energy computation platform for data-driven biomedical monitoring algorithms. | Mohammed Shoaib, Niraj K. Jha, Naveen Verma |
| 2011 | ICCD | 3D vs. 2D analysis of FinFET logic gates under process variations. | Sourindra Chaudhuri, Niraj K. Jha |
| 2010 | DATE | Low-power FinFET circuit synthesis using surface orientation optimization. | Prateek Mishra, Niraj K. Jha |
| 2009 | DATE | An architecture for secure software defined radio. | Chunxiao Li, Anand Raghunathan, Niraj K. Jha |
| 2009 | HPCA | In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. | Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha |
| 2009 | ICCD | Pragmatic design of gated-diode FinFET DRAMs. | Ajay N. Bhoj, Niraj K. Jha |
| 2009 | ICCD | FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. | Chun-Yi Lee, Niraj K. Jha |
| 2009 | ISPASS | GARNET: A detailed on-chip network model inside a full-system simulator. | Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha |
| 2009 | ITC | Thermal characterization of BIST, scan design and sequential test methodologies. | Muzaffer O. Simsir, Niraj K. Jha |
| 2009 | MICRO | In-network coherence filtering: snoopy coherence without broadcasts. | Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha |
| 2008 | DIMVA | Dynamic Binary Instrumentation-Based Framework for Malware Defense. | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha |
| 2008 | MICRO | Token flow control. | Amit Kumar, Li-Shiuan Peh, Niraj K. Jha |
| 2008 | VLSID | Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. | Anish Muttreja, Prateek Mishra, Niraj K. Jha |
| 2008 | VLSID | Variability-Tolerant Register-Transfer Level Synthesis. | Anish Muttreja, Srivaths Ravi, Niraj K. Jha |
| 2008 | VLSID | Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rtteler, Niraj K. Jha |
| 2007 | DAC | NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. | Wei Zhang, Li Shang, Niraj K. Jha |
| 2007 | DATE | Energy and execution time analysis of a software-based trusted platform module. | Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2007 | ICCD | A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. | Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha |
| 2007 | ICCD | CMOS logic design with independent-gate FinFETs. | Anish Muttreja, Niket Agarwal, Niraj K. Jha |
| 2007 | ISCA | Express virtual channels: towards the ideal interconnection fabric. | Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha |
| 2007 | VLSID | Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha |
| 2006 | DAC | Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. | Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar |
| 2006 | DAC | HybDTM: a coordinated hardware-software approach for dynamic thermal management. | Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha |
| 2006 | DAC | NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. | Wei Zhang, Niraj K. Jha, Li Shang |
| 2006 | DATE | Architectures for efficient face authentication in embedded systems. | Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2006 | DATE | Test generation for combinational quantum cellular automata (QCA) circuits. | Pallav Gupta, Niraj K. Jha, Loganathan Lingappan |
| 2006 | DATE | Satisfiability-based framework for enabling side-channel attacks on cryptographic software. | Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee |
| 2006 | ISCC | Active Learning Driven Data Acquisition for Sensor Networks. | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2006 | VLSID | Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. | Loganathan Lingappan, Niraj K. Jha |
| 2006 | VLSID | Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
| 2006 | VLSID | Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2006 | VLSID | State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. | Rui Zhang, Niraj K. Jha |
| 2005 | DAC | Efficient fingerprint-based user authentication for embedded systems. | Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | DAC | Hybrid simulation for embedded software energy estimation. | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2005 | DAC | User-perceived latency driven voltage scaling for interactive applications. | Le Yan, Lin Zhong, Niraj K. Jha |
| 2005 | DATE | Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | EUC | Nanotechnology in the Service of Embedded and Ubiquitous Computing. | Niraj K. Jha |
| 2005 | ICCD | ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. | Wei Zhang, Niraj K. Jha |
| 2005 | MASCOTS | Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach. | Le Yan, Lin Zhong, Niraj K. Jha |
| 2005 | Mobisys | Energy efficiency of handheld computer interfaces: limits, characterization and practice. | Lin Zhong, Niraj K. Jha |
| 2005 | VLSID | Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. | Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar |
| 2005 | VLSID | Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | VLSID | Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. | Rui Zhang, Pallav Gupta, Niraj K. Jha |
| 2005 | VTS | Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. | Loganathan Lingappan, Niraj K. Jha |
| 2004 | DAC | Automated energy/performance macromodeling of embedded software. | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2004 | DATE | Synthesis of Reversible Logic. | Abhinav Agrawal, Niraj K. Jha |
| 2004 | DATE | An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. | Pallav Gupta, Niraj K. Jha |
| 2004 | DATE | Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. | Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha |
| 2004 | ICCAD | High-level synthesis using computation-unit integrated memories. | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2004 | ICCAD | Power estimation for cycle-accurate functional descriptions of hardware. | Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2004 | ICCD | An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. | Pallav Gupta, Rui Zhang, Niraj K. Jha |
| 2004 | MASCOTS | An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers. | Yunsi Fei, Lin Zhong, Niraj K. Jha |
| 2004 | MICRO | Thermal Modeling, Characterization and Management of On-Chip Networks. | Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha |
| 2004 | VLSID | Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2004 | VLSID | Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. | Weidong Wang, Anand Raghunathan, Niraj K. Jha |
| 2004 | VLSID | Dynamic Power Optimization of Interactive Systems. | Lin Zhong, Niraj K. Jha |
| 2003 | CASES | Graphical user interface energy characterization for handheld computers. | Lin Zhong, Niraj K. Jha |
| 2003 | DATE | Energy Estimation for Extensible Processors. | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | DATE | Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. | Jiong Luo, Li-Shiuan Peh, Niraj K. Jha |
| 2003 | DATE | Software Architectural Transformations: A New Approach to Low Energy Embedded Software. | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
| 2003 | HPCA | Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. | Li Shang, Li-Shiuan Peh, Niraj K. Jha |
| 2003 | ICCAD | A High-level Interconnect Power Model for Design Space Exploration. | Pallav Gupta, Lin Zhong, Niraj K. Jha |
| 2003 | ICCAD | Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | ICCAD | A Scalable Application-Specific Processor Synthesis Methodology. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | ICCAD | Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. | Le Yan, Jiong Luo, Niraj K. Jha |
| 2003 | ICCD | Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. | Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha |
| 2003 | ICS | PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks. | Li Shang, Li-Shiuan Peh, Niraj K. Jha |
| 2003 | ISLPED | Analyzing the energy consumption of security protocols. | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | VLSID | Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2003 | VLSID | Task Graph Extraction for Embedded System Synthesis. | Keith S. Vallerio, Niraj K. Jha |
| 2003 | VLSID | High-level Synthesis of Multi-process Behavioral Descriptions. | Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey |
| 2002 | HiPC | Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. | Jiong Luo, Niraj K. Jha |
| 2002 | ICCAD | High-level synthesis of distributed logic-memory architectures. | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2002 | ICCAD | Synthesis of custom processors based on extensible platforms. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2002 | ICCAD | Interconnect-aware high-level synthesis for low power. | Lin Zhong, Niraj K. Jha |
| 2002 | ICCD | Embedded Operating System Energy Analysis and Macro-Modeling. | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
| 2002 | ICCD | Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. | Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha |
| 2002 | ISCAS | Task graph transformation to aid system synthesis. | Keith S. Vallerio, Niraj K. Jha |
| 2002 | VLSID | Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. | Yunsi Fei, Niraj K. Jha |
| 2002 | VLSID | Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2002 | VLSID | Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. | Li Shang, Niraj K. Jha |
| 2002 | VLSID | Input Space Adaptive Embedded Software Synthesis. | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
| 2001 | DAC | Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2001 | DAC | High-level Software Energy Macro-modeling. | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
| 2001 | DAC | Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
| 2001 | ICCAD | Low Power System Scheduling and Synthesis. | Niraj K. Jha |
| 2001 | ICCD | High-Level Power Modeling of CPLDs and FPGAs. | Li Shang, Niraj K. Jha |
| 2001 | ITC | Fast test generation for circuits with RTL and gate-level views. | Srivaths Ravi, Niraj K. Jha |
| 2001 | VLSID | Synthesis of System-on-a-chip for Testability. | Srivaths Ravi, Niraj K. Jha |
| 2000 | DAC | Power analysis of embedded operating systems. | Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha |
| 2000 | ICCAD | Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2000 | ICCD | Leakage Power Analysis and Reduction during Behavioral Synthesis. | Kamal S. Khouri, Niraj K. Jha |
| 2000 | ICCD | A Technique for Identifying RTL and Gate-Level Correspondences. | Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana |
| 2000 | ITC | : Reducing test application time in high-level test generation. | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha |
| 2000 | VLSID | COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. | Robert P. Dick, Niraj K. Jha |
| 2000 | VLSID | Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. | Kamal S. Khouri, Niraj K. Jha |
| 1999 | DAC | Common-Case Computation: A High-Level Technique for Power and Performance Optimization. | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey |
| 1999 | DATE | MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. | Robert P. Dick, Niraj K. Jha |
| 1999 | ICCAD | Memory binding for performance optimization of control-flow intensive behaviors. | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha |
| 1999 | ICCAD | A framework for testing core-based systems-on-a-chip. | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha |
| 1999 | VTS | TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | DAC | A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. | Indradeep Ghosh, Sujit Dey, Niraj K. Jha |
| 1998 | DAC | A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. | Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik |
| 1998 | DAC | Untitled record | Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | DAC | Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. | Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | DAC | Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha |
| 1998 | DATE | CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. | Bharat P. Dave, Niraj K. Jha |
| 1998 | DATE | IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | ICCAD | CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. | Robert P. Dick, Niraj K. Jha |
| 1998 | ICCAD | Transforming control-flow intensive designs to facilitate power management. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
| 1998 | ICCAD | Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | ISLPED | Fast high-level power estimation for control-flow intensive design. | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | ITC | TAO: regular expression based high-level testability analysis and optimization. | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | VLSID | COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. | Bharat P. Dave, Niraj K. Jha |
| 1998 | VLSID | A Power Management Methodology for High-Level Synthesis. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
| 1997 | DAC | COSYN: Hardware-Software Co-Synthesis of Embedded Systems. | Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha |
| 1997 | DAC | Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1997 | DAC | Power Management Techniques for Control-Flow Intensive Designs. | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi |
| 1997 | ICCAD | MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. | Robert P. Dick, Niraj K. Jha |
| 1997 | ICCAD | Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. | Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha |
| 1997 | ITC | A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. | Indradeep Ghosh, Niraj K. Jha, Sujit Dey |
| 1996 | DAC | Glitch Analysis and Reduction in Register Transfer Level. | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | ICCAD | A design for testability technique for RTL circuits using control/data flow extraction. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1996 | ICCAD | Register-transfer level estimation techniques for switching activity and power consumption. | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | ISLPED | Controller re-specification to minimize switching activity in controller/data path circuits. | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi |
| 1996 | VTS | Hardware-Software Co-Design for Test: It's the Last Straw! | J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard |
| 1995 | ICCAD | An iterative improvement algorithm for low power data path synthesis. | Anand Raghunathan, Niraj K. Jha |
| 1995 | ICCD | Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1995 | ICPP | Task Allocation for Safety and Reliability in Distributed Systems. | Santhanam Srinivasan, Niraj K. Jha |
| 1995 | ISCAS | An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. | Anand Raghunathan, Niraj K. Jha |
| 1995 | VLSID | Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
| 1994 | ICCD | Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. | Sandeep Bhatia, Niraj K. Jha |
| 1994 | ICCD | Behavioral Synthesis for low Power. | Anand Raghunathan, Niraj K. Jha |
| 1994 | ISCAS | Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. | Shalini Yajnik, Niraj K. Jha |
| 1994 | ISCAS | Synthesis of Fault Tolerant Architectures for Molecular Dynamics. | Shalini Yajnik, Niraj K. Jha |
| 1993 | DAC | Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. | Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf |
| 1993 | ICCD | Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. | Sandeep Bhatia, Niraj K. Jha |
| 1993 | ICCD | Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. | Santhanam Srinivasan, Niraj K. Jha |
| 1993 | ICPP | Design of Algorithm-Based Fault Tolerant Systems With In-System Checks. | Shalini Yajnik, Niraj K. Jha |
| 1993 | ITC | A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. | Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf |
| 1993 | VLSID | Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. | Sandeep Bhatia, Niraj K. Jha |
| 1992 | ICCAD | Behavioral synthesis for easy testability in data path scheduling. | Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha |
| 1992 | ICCD | Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. | Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka |
| 1992 | ICCD | Behavioral Synthesis for Easy Testability in Data Path Allocation. | Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha, John M. Acken |
| 1992 | VTS | A totally self-checking checker for a parallel unordered coding scheme. | Steven W. Burns, Niraj K. Jha |
| 1991 | ICCD | Design and Synthesis of Self-Checking VLSI Circuits and Systems. | Niraj K. Jha, Sying-Jyan Wang |
| 1990 | ICCD | Design of robustly testable static CMOS parity trees derived from binary decision diagrams. | Niraj K. Jha, Carol Q. Tong |
| 1989 | ICCD | Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes. | Niraj K. Jha |
| 1988 | ICCAD | On the design of robust multiple fault testable CMOS combinational logic circuits. | Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha |
| 1988 | ICCD | A new class of symmetric error correcting / unidirectional error detecting codes. | Niraj K. Jha |
| 1986 | ITC | Detecting Multiple Faults in CMOS Circuits. | Niraj K. Jha |