Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
VLSID
/
Paper
Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations.
Yang Yang
,
Niraj K. Jha
Venue
National
VLSID
Year
2013
Proceedings
VLSI Design
DBLP record
conf/vlsid/YangJ13 ↗
Browse the full
VLSID paper archive
.