Sourindra Chaudhuri
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2011–2016
Best venue rank
National
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | VLSID | Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. | Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha |
| 2014 | VLSID | FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. | Sourindra Chaudhuri, Niraj K. Jha |
| 2012 | VLSID | Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. | Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha |
| 2011 | ICCD | 3D vs. 2D analysis of FinFET logic gates under process variations. | Sourindra Chaudhuri, Niraj K. Jha |