Akshay Muraleedharan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2019–2020
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | DSD | Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. | T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese |
| 2019 | VLSID | A 75-W 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application. | Kundan Kumar, Raghunath K. P, Akshay Muraleedharan, Javed S. Gaggatur, Gaurab Banerjee |