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Paper
Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA.
T. Gokulan
,
Akshay Muraleedharan
,
Kuruvilla Varghese
Venue
C
DSD
Year
2020
Proceedings
DSD
DBLP record
conf/dsd/GokulanMV20 ↗
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