| 2023 | VLSID | Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core. | Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese |
| 2022 | DSD | High-Level Synthesis of Geant4 Particle Transport Application for FPGA. | Ramakant Joshi, Kuruvilla Varghese |
| 2022 | VLSID | A Soft RISC-V Vector Processor for Edge-AI. | V. Naveen Chander, Kuruvilla Varghese |
| 2022 | VLSID | Hardware Accelerator for Capsule Network based Reinforcement Learning. | Dola Ram, Suraj Panwar, Kuruvilla Varghese |
| 2021 | COMSNETS | Network Emulation For Tele-driving Application Development. | Srikrishna Acharya, S. Sadgun S. Devanahalli, Alok Rawat, Kuruvilla Varghese, Pratik Sharma, Bharadwaj Amrutur, Ashish Joglekar, Raghu Krishnapuram, Yogesh Simmhan, Himanshu Tyagi |
| 2020 | DSD | Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. | T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese |
| 2018 | DSD | FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training. | Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese |
| 2016 | VLSID | A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. | Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa |
| 2012 | VLSID | HD Resolution Intra Prediction Architecture for H.264 Decoder. | Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese |
| 2010 | BIBE | Space Efficient Diagonal Linear Space Sequence Alignment. | Gandhi Arpit, Raghavendra Adiga, Kuruvilla Varghese |
| 2010 | DSD | In-channel Flow Control Scheme for Network-on-Chip. | Vrishali Vijay Nimbalkar, Kuruvilla Varghese |
| 2008 | FCCM | A Scalable High Throughput Firewall in FPGA. | Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese |