Amit Khanuja
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2014–2019
Best venue rank
National
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | VLSID | Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler. | Vinay Kumar, Neeraj Kapoor, Sudhir Kumar, Monila Juneja, Amit Khanuja |
| 2017 | ISCAS | A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision. | Prashant Dubey, Kritika Aditya, Ankur Srivastava, Amit Khanuja, Jamil Kawa, Thu Nguyen |
| 2015 | VLSID | Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs. | M. Sultan M. Siddiqui, Shailendra Sharad, Yogendra Sharma, Amit Khanuja |
| 2014 | VLSID | A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. | Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja |