Amit Sanghani
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
2
Active years
2011–2016
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | VTS | Test method and scheme for low-power validation in modern SOC integrated circuits. | Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur |
| 2016 | VTS | Flexible scan interface architecture for complex SoCs. | Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn |
| 2016 | VTS | Dynamic docking architecture for concurrent testing and peak power reduction. | Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha |
| 2016 | VTS | A programmable method for low-power scan shift in SoC integrated circuits. | Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani |
| 2011 | DATE | A clock-gating based capture power droop reduction methodology for at-speed scan testing. | Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu |
| 2011 | VTS | Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. | Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu |