| 2024 | ISCAS | SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. | Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu |
| 2023 | ISCAS | Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight. | Abhishek Acharya, Anand Bulusu |
| 2023 | VLSID | An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. | Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu |
| 2023 | VLSID | Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. | Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta |
| 2022 | ISCAS | A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. | Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu |
| 2022 | ISCAS | Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. | Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta |
| 2022 | VLSID | Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. | Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta |
| 2021 | ISCAS | Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. | Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta |
| 2016 | VLSID | FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. | Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu |
| 2014 | VLSID | Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. | Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta |