| 2025 | DAC | NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. | Hanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna |
| 2025 | HPCA | CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. | Zishen Wan, Hanchen Yang, Ritik Raj, Che-Kai Liu, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna |
| 2025 | ISPASS | SCALE-Sim V3: a Modular Cycle-Accurate Systolic Accelerator Simulator for End-To-End System Analysis. | Ritik Raj, Sarbartha Banerjee, Nikhil Chandra, Zishen Wan, Jianming Tong, Ananda Samajdar, Tushar Krishna |
| 2024 | ISPASS | Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI. | Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Ananda Samajdar, Yingyan Celine Lin, Tushar Krishna, Arijit Raychowdhury |
| 2023 | DATE | AIrchitect: Automating Hardware Architecture and Mapping Optimization. | Ananda Samajdar, Jan Moritz Joseph, Tushar Krishna |
| 2022 | DAC | Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. | Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna |
| 2021 | DAC | RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. | Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna |
| 2020 | HPCA | SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training. | Eric Qin, Ananda Samajdar, Hyoukjun Kwon, Vineet Nadella, Sudarshan Srinivasan, Dipankar Das, Bharat Kaul, Tushar Krishna |
| 2020 | ISPASS | CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices. | Parth Mannan, Ananda Samajdar, Tushar Krishna |
| 2020 | ISPASS | A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim. | Ananda Samajdar, Jan Moritz Joseph, Yuhao Zhu, Paul N. Whatmough, Matthew Mattina, Tushar Krishna |
| 2019 | FPL | Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. | Ananda Samajdar, Tushar Garg, Tushar Krishna, Nachiket Kapre |
| 2018 | ASPLOS | MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects. | Hyoukjun Kwon, Ananda Samajdar, Tushar Krishna |
| 2018 | MICRO | GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware. | Ananda Samajdar, Parth Mannan, Kartikay Garg, Tushar Krishna |