Andr Seffrin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
2009–2012
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | FPGA | Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only). | Andr Seffrin, Sorin A. Huss |
| 2012 | FPL | Bil: A tool-chain for bitstream reverse-engineering. | Florian Benz, Andr Seffrin, Sorin A. Huss |
| 2011 | DDECS | Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms. | Andr Seffrin, Sorin A. Huss |
| 2011 | TrustCom | Ensuring Secure Information Flow in Partially Reconfigurable Architectures by Means of Process Algebra Analysis. | Andr Seffrin, Sorin A. Huss |
| 2010 | FDL | Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes. | Andr Seffrin, Alexander Biedermann, Sorin A. Huss |
| 2009 | FDL | DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code. | H. Gregor Molter, Andr Seffrin, Sorin Alexander Huss |