Andrew C. Ling
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
13
Venues
7
Active years
2005–2022
Best venue rank
A*
Where they publish
Papers
13 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | DSN | Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming Processors. | Dennis Abts, Ibrahim Ahmed, Andrew Bitar, Matthew Boyd, John Kim, Garrin Kimmell, Andrew C. Ling |
| 2022 | ISCA | A software-defined tensor streaming multiprocessor for large-scale machine learning. | Dennis Abts, Garrin Kimmell, Andrew C. Ling, John Kim, Matthew Boyd, Andrew Bitar, Sahil Parmar, Ibrahim Ahmed, Roberto DiCecco, David Han, John Thompson, Michael Bye, Jennifer Hwang, Jeremy Fowers, Peter Lillian, Ashwin Murthy, Elyas Mehtabuddin, Chetan Tekur, Thomas Sohmers, Kris Kang, Stephen Maresh, Jonathan Ross |
| 2018 | FPGA | In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). | Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu |
| 2018 | FPL | DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. | Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu |
| 2018 | FPL | In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. | Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev |
| 2017 | FPGA | An OpenCL™ Deep Learning Accelerator on Arria 10. | Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu |
| 2013 | FPGA | Harnessing the power of FPGAs using altera's OpenCL compiler. | Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling |
| 2010 | FPGA | Towards scalable placement for FPGAs. | Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu |
| 2009 | FPGA | Towards automated ECOs in FPGAs. | Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour |
| 2007 | ASPDAC | BddCut: Towards Scalable Symbolic Cut Enumeration. | Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown |
| 2005 | DAC | FPGA technology mapping: a study of optimality. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | FPL | FPGA PLB Evaluation using Quantified Boolean Satisfiability. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | SAT | FPGA Logic Synthesis Using Quantified Boolean Satisfiability. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |