| 2026 | DATE | From Cloud-Heavy to Edge-Ready: Self-supervised Transfer-efficient Emotion Recognition. | Junjiao Sun, Jos Miranda, Jorge Portilla, Andrs Otero |
| 2026 | GECCO | LsmGrid: A Data-Aware Neuroevolution Framework for Designing Minimal Liquid State Machines. | Andrs Ignacio Romo, Andrs Otero, Jos Manuel Lanza-Gutirrez |
| 2025 | DATE | Solving the Cold-Start Problem for the Edge: Clustering and Adaptive Deep Learning for Emotion Detection. | Junjiao Sun, Laura Gutirrez-Martn, Celia Lpez-Ongil, Jos Miranda, Jorge Portilla, Andrs Otero |
| 2025 | DSD | Hardware-aware Decision Tree Ensembles for Radar Data Processing on the Edge with Online Learning. | Rodrigo Olmos, Pedro Lobo, Andrs Otero, Sergio Hernndez, Eduardo Casanueva |
| 2023 | ICRA | A Framework for Fast Prototyping of Photo-realistic Environments with Multiple Pedestrians. | Sara Casao, Andrs Otero, lvaro Serra-Gmez, Ana C. Murillo, Javier Alonso-Mora, Eduardo Montijano |
| 2019 | FCCM | Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. | Rafael Zamacola, Alberto Garca-Martnez, Javier Mora, Andrs Otero, Eduardo de la Torre |
| 2014 | FPL | A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. | Juan Valverde, Alfonso Rodrguez, Julio Camarero, Andrs Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2013 | FPL | A self-adaptive image processing application based on evolvable and scalable hardware. | Angel Gallego, Javier Mora, Andrs Otero, Blanca Lpez, Eduardo de la Torre, Teresa Riesgo |
| 2012 | FPL | On the automatic integration of hardware accelerators into FPGA-based embedded systems. | Christian Pilato, Andrea Cazzaniga, Gianluca Durelli, Andrs Otero, Donatella Sciuto, Marco D. Santambrogio |
| 2012 | FPL | Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. | Rubn Salvador, Andrs Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Luks Sekanina |
| 2011 | FPL | Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. | Andrs Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastin Lpez, Gustavo M. Callic, Roberto Sarmiento |
| 2010 | DSD | A Modular Peripheral to Support Self-Reconfiguration in SoCs. | Andrs Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2010 | FPL | Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. | Andrs Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva |