Angshuman Parashar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
19
Venues
8
Active years
2004–2024
Best venue rank
A*
Where they publish
Papers
19 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | ISCA | Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms. | Qijing Huang, Po-An Tsai, Joel S. Emer, Angshuman Parashar |
| 2023 | ISPASS | LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. | Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2023 | MICRO | HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. | Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2022 | DATE | DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. | Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna |
| 2022 | ISPASS | Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. | Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi |
| 2022 | MICRO | Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. | Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2022 | SIGMETRICS | A Formalism of DNN Accelerator Flexibility. | Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna |
| 2021 | ASPLOS | Mind mappings: enabling efficient algorithm-accelerator mapping space search. | Kartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W. Fletcher |
| 2021 | ISPASS | Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. | Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2019 | ISPASS | Timeloop: A Systematic Approach to DNN Accelerator Evaluation. | Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer |
| 2019 | MICRO | Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. | Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna |
| 2017 | ISCA | SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. | Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally |
| 2013 | ISCA | Triggered instructions: a control paradigm for spatially-programmed architectures. | Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer |
| 2012 | FPGA | Leveraging latency-insensitivity to ease multiple FPGA design. | Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer |
| 2011 | FPGA | Leap scratchpads: automatic memory and cache management for reconfigurable logic. | Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer |
| 2011 | HPCA | HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. | Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer |
| 2007 | ISCA | Mechanisms for bounding vulnerabilities of processor structures. | Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam |
| 2006 | ASPLOS | SlicK: slice-based locality exploitation for efficient redundant multithreading. | Angshuman Parashar, Anand Sivasubramaniam, Sudhanva Gurumurthi |
| 2004 | ISCA | A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. | Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam |