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Antonio Nez

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

5

Active years

1993–2013

Best venue rank

A

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2013DSDScalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology.Pedro P. Carballo, Omar Espino, Romn Neris, Pedro Hernandez-Fernandez, Tomasz Szydzik, Antonio Nez
2011ISMA Low Memory Requirements Execution Flow for the Non-Uniform Grid Projection Super-Resolution Algorithm.Tomasz Szydzik, Gustavo M. Callic, Antonio Nez
2006DATEA unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study.Vctor Reyes, Wido Kruijtzer, Toms Bautista, Ghiath Alkadi, Antonio Nez
2006DSDVIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems.Armando Snchez-Pea, Pedro P. Carballo, Luz Garca, Antonio Nez
2005ISCASLow-cost implementation of a super-resolution algorithm for real-time video applications.Sebastin Lpez, Gustavo M. Callic, Jos Francisco Lpez, Roberto Sarmiento, Antonio Nez
2001ISCASA compact layout technique to minimize high frequency switching effects in high speed circuits.Juan A. Montiel-Nelson, De de Armas, Roberto Sarmiento, Antonio Nez, Saeid Nooshabadi
2000DATEA Single Phase Latch for High Speed GaAs Domino Circuits.Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Nez, Roberto Sarmiento, Javier Sosa
1999DATEHigh Speed GaAs Subsystem Design using Feed Through Logic.Juan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Nez
1998DATEA Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design.Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Nez
1993PDPUsing the ES2 library and SILOS simulator in the development of a single chip with three processors and analog IO.Juan A. Montiel-Nelson, Valentin de Armas, D. Q. M. Fay, Antonio Nez