Ashok Jagannathan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
6
Active years
2000–2026
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | VLSID | Cost and Communication-Aware Fast Placement of Processing Elements in Chiplets for 2.5D Systems. | Ayman Un Nisa, Ashok Jagannathan, Sumit K. Mandal |
| 2017 | ISCA | ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks. | Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan |
| 2014 | ASPDAC | Array scalarization in high level synthesis. | Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan |
| 2006 | ASPDAC | An automated design flow for 3D microarchitecture evaluation. | Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang |
| 2005 | ASPDAC | Microarchitecture evaluation with floorplanning and interconnect pipelining. | Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong |
| 2005 | FPGA | Instruction set extension with shadow registers for configurable processors. | Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang |
| 2005 | ISLPED | Understanding the energy efficiency of SMT and CMP with multiclustering. | Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir |
| 2003 | DAC | Microarchitecture evaluation with physical planning. | Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis |
| 2000 | DAC | A fast algorithm for context-aware buffer insertion. | Ashok Jagannathan, Sung-Woo Hur, John Lillis |