| 2014 | HPCC | An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. | Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi |
| 2009 | ISCAS | A Neural Signal Detection Amplifier with Low-frequency Noise Suppression. | Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu |
| 2008 | GLOBECOM | High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications. | Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata |
| 2008 | HOTI | High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections. | Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata |
| 2008 | SIGCOMM | Off-the-path flow handling mechanism forhigh-speed and programmable traffic management. | Hideyuki Shimonishi, Takashi Yoshikawa, Atsushi Iwata |
| 2007 | NCA | Multilayer In-service Reconfiguration for Network Computing Systems. | Nobuharu Kami, Jun Suzuki, Yoichi Hidaka, Takashi Yoshikawa, Atsushi Iwata |
| 2006 | ACCV | Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes. | Kan'ya Sasaki, Seiji Kameda, Atsushi Iwata |
| 2006 | HOTI | ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform. | Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata |
| 2005 | ICNC | A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. | Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata |
| 2005 | ISCAS | A 1V supply successive approximation ADC with rail-to-rail input voltage range. | Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata |
| 2004 | GLOBECOM | Design of multiple reverse spanning trees in next generation of Ethernet-VPNs. | Aleksandar Kolarov, Bhaskar Sengupta, Atsushi Iwata |
| 2004 | KES | A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. | Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata |
| 2003 | KES | A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. | Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata |
| 2002 | GLOBECOM | Coarse-grain dynamic replication schemes for scalable content delivery networks. | Norihito Fujita, Nobuyuki Enomoto, Atsushi Iwata, Rauf Izmailov |
| 2002 | VLSID | Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. | Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata |
| 2001 | ASPDAC | Test circuits for substrate noise evaluation in CMOS digital ICs. | Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata |
| 2001 | GLOBECOM | Adaptive and efficient multiple path pre-computation for QoS routing protocols. | Norihito Fujita, Atsushi Iwata |
| 2000 | ASPDAC | An arbitrary chaos generator core curcuit using PWM/PPM signals. | Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata |
| 2000 | ASPDAC | Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. | Makoto Nagata, Atsushi Iwata |
| 2000 | ASPDAC | A smart imager for the vision processing front-END. | Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata |
| 2000 | ISCAS | Pulse modulation circuit architecture and its application to functional image sensors. | Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie |
| 1998 | ICONIP | Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. | Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata |
| 1998 | ICONIP | Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. | Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata |
| 1986 | ICASSP | A 50ns floating-point signal processor VLSI. | Takao Kaneko, Hironori Yamauchi, Atsushi Iwata |
| 1986 | ICASSP | VLSI- A to D and D to A converters with multi-stage noise shaping modulators. | Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata |
| 1985 | ICASSP | An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM. | Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono |
| 1982 | ICASSP | A high quality ADM LSI codec at 32 kbit/s for digital speech communications. | Naohisa Ohta, Kazunari Irie, Takehiko Uno, Atsushi Iwata, Tomonori Aoyama |