| 2026 | ASPDAC | Analysis and Design of Oblong Coils and Standard-Cell-Based Receiver for Area-Efficient Edge-Coupled Inductive Coupling Transceiver. | Yuki Mitarai, Mototsugu Hamada, Atsutake Kosuge |
| 2026 | ISCAS | A 3-day ASIC Design Hands-on with the Minimal Fab. | Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda |
| 2025 | ASPDAC | A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. | Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge |
| 2025 | ISCAS | An SoC Design and Fabrication Hands-On Educational Course within One Week Using Structured ASIC. | Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda |
| 2025 | ISCAS | A 83.7% Resource Reduced FPGA-based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT. | Yuxuan Pan, Mototsugu Hamada, Atsutake Kosuge |
| 2024 | ISCAS | Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. | Dongzhu Li, Tianqi Zhao, Kenji Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | ASPDAC | A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. | Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | ASPDAC | A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. | Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | ISCAS | A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. | Dongzhu Li, Yao-Chung Hsu, Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | IECON | An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. | Eitaro Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2022 | ASPDAC | A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. | Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2019 | FCCM | A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications. | Atsutake Kosuge, Keisuke Yamamoto, Yukinori Akamine, Taizo Yamawaki, Takashi Oshima |
| 2016 | ASPDAC | Analytical thruchip inductive coupling channel design optimization. | Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda |
| 2015 | ASPDAC | Design and analysis for ThruChip design for manufacturing (DFM). | Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda |
| 2015 | ASPDAC | Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. | Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda |
| 2013 | ASPDAC | A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. | Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda |