B. Suresh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2000–2005
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | VLSID | Application of Alpha Power Law Models to PLL Design Methodology. | B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni |
| 2003 | ICCS | Object Oriented Parallel Programming Model on a Network of Workstations. | B. Suresh, R. Nadarajan |
| 2000 | VLSID | Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. | B. Suresh, Biswadeep Chaterjee, R. Harinath |