| 2026 | ISMIS | T-HiGra: Temporal Reasoning over Hierarchical Knowledge Graphs for Time-Constrained Open-Domain QA. | Bao Le, Anh Nguyen, Hung Luu, Tho Quan |
| 2023 | ACIVS | A Deep Learning Approach to Segment High-Content Images of the E. coli Bacteria. | Dat Q. Duong, Tuan-Anh Tran, Phuong Nhi Nguyen Kieu, Tien K. Nguyen, Bao Le, Stephen Baker, Binh T. Nguyen |
| 2014 | ASPDAC | Automated debugging of missing assumptions. | Brian Keng, Evean Qin, Andreas G. Veneris, Bao Le |
| 2014 | ICCAD | Multiple clock domain synchronization in a QBF-based verification environment. | Djordje Maksimovic, Bao Le, Andreas G. Veneris |
| 2013 | ASPDAC | Reviving erroneous stability-based clock-gating using partial Max-SAT. | Bao Le, Dipanjan Sengupta, Andreas G. Veneris |
| 2013 | IOLTS | Accelerating post silicon debug of deep electrical faults. | Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos |
| 2012 | DATE | Non-solution implications using reverse domination in a modern SAT-based debugging environment. | Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris |
| 2012 | DATE | Leveraging reconfigurability to raise productivity in FPGA functional debug. | Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le |
| 2010 | DATE | Leveraging dominators for preprocessing QBF. | Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus |