| 2026 | ISCAS | An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems. | Yilmaz Ege Gonul, Baris Taskin |
| 2025 | DATE | A Multi-Stage Potts Machine Based on Coupled CMOS Ring Oscillators. | Yilmaz Ege Gonul, Baris Taskin |
| 2024 | ICCAD | Multi-phase Coupled CMOS Ring Oscillator based Potts Machine. | Yilmaz Ege Gonul, Baris Taskin |
| 2024 | ISCAS | Design Automation for Charge Recovery Logic. | Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin |
| 2024 | ISCAS | High-Speed Phase-Based Computing. | Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin |
| 2022 | ISCAS | A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators. | Ragh Kuttappa, Baris Taskin |
| 2022 | ISCAS | Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. | Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan |
| 2020 | HPCA | SnackNoC: Processing in the Communication Layer. | Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, Mark Hempstead |
| 2020 | ISCAS | Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking. | Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin |
| 2020 | ISCAS | FinFET - Based Low Swing Rotary Traveling Wave Oscillators. | Ragh Kuttappa, Baris Taskin |
| 2019 | ISCAS | Low Swing - Low Frequency Rotary Traveling Wave Oscillators. | Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin |
| 2019 | ISLPED | Robust Low Power Clock Synchronization for Multi-Die Systems. | Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis |
| 2019 | MICRO | On-chip wireless interconnect paradigm. | Baris Taskin |
| 2018 | ISCAS | A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion. | Leo Filippini, Baris Taskin |
| 2018 | ISCAS | Low Frequency Rotary Traveling Wave Oscillators. | Ragh Kuttappa, Baris Taskin |
| 2018 | ISCAS | NoC Router Lifetime Improvement using Per-Port Router Utilization. | Scott Lerner, Vasil Pano, Baris Taskin |
| 2018 | ISCAS | Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. | Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin |
| 2018 | ISPASS | Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces. | Michael Lui, Karthik Sangaiah, Mark Hempstead, Baris Taskin |
| 2017 | DATE | Reconfigurable threshold logic gates using optoelectronic capacitors. | Ragh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin |
| 2017 | ISCAS | Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. | Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin |
| 2016 | ICCD | Wireless Network-on-Chip analysis of propagation technique for on-chip communication. | Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin, Kapil R. Dandekar |
| 2016 | ICCD | Energy aware routing of multi-level Network-on-Chip traffic. | Vasil Pano, Isikcan Yilmaz, Ankit More, Baris Taskin |
| 2016 | ISCAS | Charge recovery logic for thermal harvesting applications. | Leo Filippini, Baris Taskin |
| 2016 | ISCAS | Exploiting useful skew in gated low voltage clock trees. | Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin |
| 2015 | ICCAD | Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling. | Karthik Sangaiah, Mark Hempstead, Baris Taskin |
| 2015 | ICCD | A wirelessly powered system with charge recovery logic. | Leo Filippini, Emre Salman, Baris Taskin |
| 2015 | ISCAS | Enhanced level shifter for multi-voltage operation. | Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin |
| 2015 | ISPASS | Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation. | Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead |
| 2015 | VLSID | Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. | Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin |
| 2015 | VLSID | Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping. | Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More |
| 2014 | ICCAD | Frequency-centric resonant rotary clock distribution network design. | Ying Teng, Baris Taskin |
| 2014 | ICCD | Static thread mapping for NoCs via binary instrumentation traces. | Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More |
| 2014 | ICCD | Timing characterization of clock buffers for clock tree synthesis. | Can Sitik, Scott Lerner, Baris Taskin |
| 2013 | DATE | Sparse-rotary oscillator array (SROA) design for power and skew reduction. | Ying Teng, Baris Taskin |
| 2013 | ICCD | Resonant frequency divider design methodology for dynamic frequency scaling. | Ying Teng, Baris Taskin |
| 2012 | ICCAD | High-Performance, Low-Power Resonant Clocking: Embedded tutorial. | Matthew R. Guthaus, Baris Taskin |
| 2012 | ICCAD | Clock mesh synthesis with gated local trees and activity driven register clustering. | Jianchao Lu, Xiaomi Mao, Baris Taskin |
| 2012 | ICCD | Multi-voltage domain clock mesh design. | Can Sitik, Baris Taskin |
| 2012 | ICCD | Clock mesh synthesis method using the Earth Mover's Distance under transformations. | Ying Teng, Baris Taskin |
| 2012 | ISCAS | A unified design methodology for a hybrid wireless 2-D NoC. | Ankit More, Baris Taskin |
| 2012 | VLSID | 3-D Parasitic Modeling for Rotary Interconnects. | Vinayak Honkote, Ankit More, Baris Taskin |
| 2011 | DATE | Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. | Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin |
| 2011 | ICCD | EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs. | Ankit More, Baris Taskin |
| 2011 | ICCD | ROA-brick topology for rotary resonant clocks. | Ying Teng, Jianchao Lu, Baris Taskin |
| 2011 | ISCAS | Register On MEsh (ROME): A novel approach for clock mesh network synthesis. | Jianchao Lu, Yusuf Aksehir, Baris Taskin |
| 2011 | ISCAS | Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits. | Jianchao Lu, Baris Taskin |
| 2010 | ICCD | Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. | Vinayak Honkote, Baris Taskin |
| 2010 | ISLPED | PEEC based parasitic modeling for power analysis on custom rotary rings. | Vinayak Honkote, Baris Taskin |
| 2010 | VLSID | Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. | Vinayak Honkote, Baris Taskin |
| 2008 | ICCD | Custom rotary clock router. | Vinayak Honkote, Baris Taskin |
| 2004 | ISCAS | Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. | Baris Taskin, Ivan S. Kourtev |