Benjamin Stefan Devlin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2011–2011
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | ASPDAC | A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada |
| 2011 | ISLPED | Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada |