Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
ASPDAC
/
Paper
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS.
Benjamin Stefan Devlin
,
Makoto Ikeda
,
Kunihiro Asada
Venue
B
ASPDAC
Year
2011
Proceedings
ASP-DAC
DBLP record
conf/aspdac/DevlinIA11 ↗
Browse the full
ASPDAC paper archive
.