| 2017 | ASPDAC | CMOS-on-quartz pulse generator for low power applications. | Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2017 | ASPDAC | A 15 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. | Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
| 2017 | ETS | Extension of power supply impedance emulation method on ATE for multiple power domain. | Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada |
| 2016 | DATE | Analytical design optimization of sub-ranging ADC based on stochastic comparator. | Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2016 | ITC | Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. | Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada |
| 2015 | DDECS | An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. | Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
| 2014 | DDECS | Burst-pulse Generator based on transmission line toward sub-MMW. | Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada |
| 2014 | DDECS | Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. | Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada |
| 2014 | ISCAS | A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. | James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada |
| 2014 | ITC | Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. | Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada |
| 2013 | ASPDAC | High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. | Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada |
| 2013 | ITC | A novel test structure for measuring the threshold voltage variance in MOSFETs. | Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada |
| 2012 | ITC | Power integrity control of ATE for emulating power supply fluctuations on customer environment. | Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada |
| 2011 | ASPDAC | A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada |
| 2011 | ASPDAC | All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. | Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2011 | ASPDAC | A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. | Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada |
| 2011 | DDECS | An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. | Tetsuya Iizuka, Kunihiro Asada |
| 2011 | DDECS | Decoupling capacitance boosting for on-chip resonant supply noise reduction. | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada |
| 2011 | ISCAS | An equivalent-time and clocked approach for continuous-time quantization. | Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada |
| 2011 | ISLPED | Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada |
| 2011 | ITC | Application of a continuous-time level crossing quantization method for timing noise measurements. | Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu |
| 2010 | ASPDAC | Cascaded time difference amplifier using differential logic delay cell. | Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2010 | DATE | An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. | Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada |
| 2010 | DDECS | Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. | Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2009 | ASPDAC | Circuit design using stripe-shaped PMELA TFTs on glass. | Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada |
| 2009 | DDECS | Measurement of power supply noise tolerance of self-timed processor. | Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda |
| 2009 | DDECS | All digital baseband 50 Mbps data recovery using 5 oversampling with 0.9 data unit interval clock jitter tolerance. | Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2009 | ETS | Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. | Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada |
| 2007 | ASPDAC | Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. | Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2007 | DDECS | Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. | Zhicheng Liang, Makoto Ikeda, Kunihiro Asada |
| 2006 | DATE | On-chip 8GHz non-periodic high-swing noise detector. | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada |
| 2006 | DATE | Timing-driven cell layout de-compaction for yield optimization by critical area minimization. | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
| 2006 | DDECS | Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada |
| 2006 | ISCAS | Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
| 2005 | ICIP | Real-time 3-D measurement system based on light-section method using smart image sensor. | Yusuke Yachide, Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
| 2004 | ASPDAC | High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
| 2004 | ASPDAC | Design of real-time VGA 3-D image sensor using mixed-signal techniques. | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
| 2003 | ISCAS | High-speed position detector using new row-parallel architecture for fast collision prevention system. | Yusuke Oike, Makoto Ikeda, Kunihiro Asada |
| 2002 | ISCAS | Logic synthesis for PLA with 2-input logic elements. | Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada |
| 2002 | VLSID | An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. | Tohru Ishihara, Kunihiro Asada |
| 2002 | VLSID | Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. | Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada |
| 2001 | ASPDAC | A system level memory power optimization technique using multiple supply and threshold voltages. | Tohru Ishihara, Kunihiro Asada |
| 2001 | ASPDAC | A smart position sensor for 3-D measurement. | Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada |
| 2001 | ASPDAC | Finding an optimal functional decomposition for LUT-based FPGA synthesis. | Jian Qiao, Makoto Ikeda, Kunihiro Asada |
| 2001 | ASPDAC | A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. | Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada |
| 2000 | ASPDAC | A binary image sensor with flexible motion vector detection using block matching method. | Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada |
| 2000 | FPL | Optimum Functional Decomposition for LUT-Based FPGA Synthesis. | Jian Qiao, Makoto Ikeda, Kunihiro Asada |
| 1998 | ASPDAC | Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. | Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada |
| 1998 | ASPDAC | An Analysis on VLSI Interconnection Considering Skin Effect. | Tetsuhisa Mido, Kunihiro Asada |
| 1997 | ASPDAC | Crosstalk noise in high density and high speed interconnections due to inductive coupling. | Tetsuhisa Mido, Kunihiro Asada |
| 1995 | ISCAS | Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier. | Minkyu Song, Kunihiro Asada |